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MIC2555
USB - OTG Transceiver
General Description
MIC2555 is a USB On-The-Go (OTG) transceiver designed to enable intelligent self-powered devices to communicate on a peer-to-peer basis with other USB and USB OTG enabled devices. Designed to perform as a PHY for USB Serial Interface Engines (SIE), MIC2555 is compatible with a wide variety of stand-alone OTG SIE chips, OTG IP cores (used in ASIC and COT designs), and Application Specific Standard Products (ASSPs). MIC2555 is fully compliant to USB-IF's Universal Serial Bus Specification 2.0 and the On-The-Go Supplement Rev 1.0a, for Low speed and Full speed operation, and allows dual-role device (DRD) operation via an I2C based controller interface. The controller's robust register set permits full control over bus and interface activity for transacting Session Request Protocol (SRP) and Host Negation Protocol (HNP) sequences. Messaging between Host and Target devices can utilize either USB or UART signaling methods. Additionally, the MIC2555 permits audio signaling on its D+, D- and ID lines in support of analog car kit applications. USB communication is complemented with on-chip D+, Dpull-up/pull-down resistors, an integrated charge pump and low dropout voltage regulators to provide stable internal supply voltages and to supply VBUS power when operating as an A-device. Logic input levels spanning 1.6V to 4.5V ensure compatibility with current and future generations of process technology. The MIC2555 is offered in a space saving 4mm x 4mm 24pin MLFTM package. Data sheets and support documentation can be found on Micrel's web site at www.micrel.com.
Features
* * * * * Complies with USB-IF USB standard 2.0 and OTG supplement Revision 1.0a. Provides signaling and control logic for SRP and HNP, enabling USB Dual-role device operation. Designed for Full-speed and Low-speed USB communications. I2C controller interface. Offers 3 modes of operation: - USB - UART - Audio Operates with VLOGIC of 1.6V - 4.5V, assuring compatibility with low voltage ASICs. Tri-level ID detection for recognition of USB and non-USB devices. Supports USB /Car Kit audio interface. Allows Single-ended and Differential Logic I/O. Integrated charge pump for VBUS supply. On-chip pull-up, pull-down resistors minimize external component count. Suspend and Power-down modes for power conservation. Operates over the full Industrial Temperature range: -40C to +85C. Cellular Telephones PDAs Digital Still Cameras Camcorders Data Cradles CD and MP3 players Printers
* * * * * * * *
Applications
* * * * * * *
MicroLead Frame and MLF are trademarks of Amkor Technologies Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
June 2005
M9999-060805 (408) 955-1690
Micrel, Inc.
MIC2555
Ordering Information
Part Number Standard Pb-Free Address Junction Temp. Range Package
MIC2555BML-0 MIC2555BML-1
MIC2555YML-0 MIC2555YML-1
0x 1x
-40C to +85C -40C to +85C
24-pin MLFTM 24-pin MLFTM
Typical Application
VCC
System Supply Voltage
VDD
VBAT VDD_LOGIC OE_INT/ RCV MIC2555 DAT_VP_RX SE0_VM_TX SCL SDA CAP+ 0.22F CAP-
VTRM VBUS ID RS D+ D- RS
VBUS
USB SIE Controller
D+ D- GND
USB Port
GND CAP++
10F 220F
4.7F
MIC2555 Typical Application Circuit
Pin Configuration
VDD_LGC GND_A CAPVBAT CAP+ CAP++ RCV SE0_VM_TX DAT_VP_RX OE_INT/ INT/ GPIO_0_RX GPIO_1_TX SCL SDA ADR0 RESET/ GPIO_2 VTRM VBUS DD+ ID GND_D
4mm x 4mm 24-pin MLF (ML)
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MIC2555
Pin Description
Pin Number 1 2 Type O I/O Pin Name RCV SE0_VM_TX Pin Description Output from differential receiver. = SE0 in USB DAT-SE0 mode = VM in VP-VM mode. = UART Transmit output when in UART Mode See figures 1 and 2 on page 4 = DAT in USB DAT-SE0 mode. = VP in VP-VM mode = UART Receive input when in UART mode See figures 1 and 2 on page 4 A Multi-mode pin controlling various functions in conjunction with control register bits. A logic LOW on this pin gives the following results: = OE (Output Enable): Enables D+, D- as USB outputs. = INT/ (Interrupt): Active LOW output when register bits `suspend' and `oe_int_en' both = 1. Interrupt (bar). Open Drain Active LOW output. May be wire-ORed with other interrupt signals. = General purpose I/O. Open drain output. = Alternate UART Receive input. See figures 1 and 2 on page 4 = General purpose I/O. Open drain output. = Alternate UART Transmit output. See figures 1 and 2 on page 4 I2C Clock I2C Data 2 Sets Address bit A0 of I C controller. This pin is a digital input and must not be left floating. System reset. Active LOW. General purpose I/O. Open drain output. System Digital ground. Identification input. Monitors the ID pin of the USB connector and indicates both the presence of a device and type (USB or not USB). = USB D+ when in USB mode. = UART Receive in UART mode. = Right Speaker audio output in stereo mode. = Microphone signal from Car Kit. = USB D- when in USB mode. = UART Transmit out in UART mode. = Left Speaker audio output in stereo mode. = Monaural audio output to Car Kit. USB 5V power. Internal 3.3V supply. Sets USB signal levels. Positive lead for charge pump reservoir capacitor. Positive lead for charge pump capacitor. Positive voltage from battery. Supplies power to MIC2555 internal circuitry and power for charge pump when driving VBUS. Negative lead for charge pump capacitor. Analog ground. Isolated Charge Pump ground. Logic supply voltage. Used to set logic levels between MIC2555 and System Controller / ASIC.
3
I/O
DAT_VP_RX
4
I/O
OE_INT/
5 6
O I/O
INT/ GPIO_0_RX
7 8 9 10 11 12 13 14
I/O I/O I/O I I I/O I/O I/O
GPIO_1_TX SCL SDA ADR_0 RESET/ GPIO_2 GND_D ID
15
I/O
D+
16 17 18 19 20 21 22 23 24
I/O I/O I/O I I I I I I
DVBUS VTRM CAP++ CAP+ VBAT CAPGND_A VDD_LGC
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MIC2555
Interconnect Diagrams
Host Controller 1 MIC2555 SIE IC 2:1
2
SE0_VM_TX DAT_VP_RX D+ D-
UART TX RX
UART
Figure 1. Controller with Multiplexed Serial Interfaces
Host Controller 1 MIC2555 SIE I2C SE0_VM_TX DAT_VP_RX D+ D- UART GPIO_0_RX GPIO_1_TX UART TX RX
Figure 2. Controller with Parallel Serial Interfaces
NOTE 1 Examples of Host Controller are: Baseband Processor/IC Processor Modem
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MIC2555
Absolute Maximum Ratings(1)
Power Supply Voltage: VBAT, GPIO- ................................................. -0.3V to +6.0V VDD_LGC ......................................... -0.3V to +6.0V and VBAT USB Bus Voltage VBUS ......................................................................-0.3V to +6.0V VDD_LGC .........................................-0.3V to +6.0V and VBUS Voltage On Any Other Pin............................ -0.3V to +4.5V Current Into/Out of Any Pin .......................................10mA Junction Temperature ................................................ 150C Storage Temperature .................................-65C to +150C ESD Ratings:..............................................VBUS, D+, D-, ID Human Body Model .............................................. 15 kV ESD Ratings:................................................... All other pins Human Body Model ................................................ 2 kV
Operating Ratings(2)
Power Supply Voltage: VBUS .......................................................... 4.4V to 5.25V VBAT ............................................................ 3.0V to 4.5V Operating Temperature................................ -40C to +85C Package Thermal Resistance .................................. 49C/W
Electrical Characteristics(3)
Test condition is 25C unless otherwise specified. Bold indicates -40C + 85C, VBAT = 3.6V, VDD_LGC = 3.6V, VBUS = 5.0V, VTRM = 1F, C+ = 0.22F, C++ = 220F, CVBUS = 10F
Symbol Parameter Condition Min 3.0 1.6 ITRM 2.5mA, 3.0 < VBAT < 3.6V Power Down mode Suspend mode Full Speed, Idle, D+ 2.8V, D- 0.3V, IVBUS = 0mA Full Speed Transmitting 12Mb/s, CLOAD 350pF on D+, D-, IVBUS = 0mA Full Speed Transmitting 12Mb/s, CL = 50pF on D+,D-, IVBUS = 0mA Low Speed Transmitting 1.5Mb/s, CL = 350pF on D+,D-, IVBUS = 0mA Suspend mode, OE_INT/ = 1 OE_INT/ = 1 2.8 3.3 13 140 2.8 17 2.5 6.5 80 7 Typ Max 4.5 VBAT 3.6 20 250 5.0 40 6 12 100 15 Units V V V A A mA mA mA mA A A Power Supplies VBAT System Supply Voltage VDD_LGC VTRM IBAT_PD IBAT_SUS IBAT_FS_I IBAT_FS_HC IBAT_FS_LC IBAT_LS_HC IVBUS_S IVDD_LGC Logic Supply Voltage Termination Voltage (internal supply voltage) System Supply Current System Supply Current System Supply Current System Supply Current System Supply Current System Supply Current Current drawn by System from VBUS Current drawn by System for core logic Voltage Output to VBUS VBUS Output Current B device SRP Pull-up Resistor on VBUS B device SRP Pull-down Resistor on VBUS
Charge Pump and VBUS VBUS_ OUT IVBUS RVBUS_PU RVBUS_PD IBUS = 10mA, VBAT = 3.0V 4.4V VBUS 5.25V Pull-up voltage = VTRM Pull-down to GND 4.4 10 281 675 5.0 27 1300 2300 7500 7500 5.25 V mA
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MIC2555
Symbol RA_BUS_IN VTH_VBUS VTH_SV VTH_SE ID VTHH_R_ID VTHL_R_ID RID_PU IID_WPU RID_SW_GND
Parameter VBUS Input Resistance `VBUS Valid' Comparator Threshold Voltage "Session Valid' Comparator Threshold Voltage "Session End' Comparator Threshold Voltage Upper Threshold for ID Resistor Sensing Lower Threshold for ID Resistor Sensing Pull-up Resistor switched to ID for detecting non-USB devices Weak Pull-up current source driving ID pin Interrupt Pulse Switch
Condition Seen from VBUS pin to GND
Min 40 4.4 0.8 0.2
Typ 63 4.5 1.4 0.4
Max 100 4.6 2.0 0.8
Units k V V V
VBAT = 3.0V VBAT = 3.0V
2.45 0.35 70
2.55 0.42 90
2.65 0.55 130 6
V V k A k
VID = 0V VID 200mV
2 1.0
4.0
Logic Levels - SDA, SCL, ADR0, OE_INT/, SE0_VM_TX, DAT_VP_RX, RCV, INT/, RESET/ & GPIO VIL VIH LOW-Level Input Voltage HIGH-Level Input Voltage Input Hysteresis VIL VIH IIN_LGC VOL VOH VOL_SDA VOH_SDA VOL_GPIO VOH_GPIO IOH_GPIO LOW-Level Input Voltage HIGH-Level Input Voltage Input Leakage Current LOW-Level Output Voltage HIGH-Level Output Voltage LOW-Level Output Voltage at SDA pin HIGH-Level Output Voltage at SDA pin LOW-Level Output Voltage at GPIO pins HIGH-Level Output Voltage at GPIO pins GPIO Output driver leakage current ADR0, OE_INT/, SE0_VM_TX, DAT_VP_RX, RCV, INT/, RESET/ & GPIO Applies to USB and UART modes. 1.6V VDD_LGC 4.5V IOL = 100A IOH = 100A IOL = 5mA RSDA_PU = 3.0K IOL = 10mA RPU = 3.0K VDD_PU = VOH_GPIO = 5V 0.7x VDD_LGC 150 VDD_PU - 0.1V 1 250 VDD_PU 30 0.9x VDD_LGC 0.3x VDD_LGC SDA, SCL 0.7x VDD_LGC 100 0.15x VDD_LGC 0.85x VDD_LGC -5 .02 +5 0.1 0.3x VDD_LGC V V mV V V A V V V V mV V A
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MIC2555
Symbol Parameter Transceiver DC Characteristics - D+, DVDI VCM VTH_SE VHYS VOL VOH RDRV RPU_D RPD_D CIN_D VTHL_INT_HI VTHL_INT_LO Differential Input Sensitivity Differential Common-Mode Range Single-Ended Receiver Threshold Receiver Hysteresis LOW-Level Output Voltage HIGH-Level Output Voltage Transceiver Output Resistance Internal Pull-Up Resistor on D+ and DInternal Pull-Down Resistor or D+ and DTransceiver Input Capacitance Interrupt Detector Threshold HIGH Interrupt Detector Threshold LOW
Condition |(D+) - (D-)|, VIN = 0.8V - 2.5V Includes VDI Range
Min 0.2 0.8 0.8
Typ
Max
Units V
2.5 1.5 200 0.1 0.3 3.6 24 3.09 1.575 24.8 20 2.0
V V mV V V k k k pF V V
D+, DOE_INT/ = 0, RL = 1.5k to 3.6V OE_INT/ = 0, ISOURCE = 1mA D+, DVTRM to D+ or DD+ to GND, D- to GND D+, D- pins to GND See Note 4 2.5 0.3 Active Idle 2.8 5 1.425 0.900 14.3
3.3 12 2.25 1.24 19.5
3.0 0.5
3.3 0.7
Transceiver AC Characteristics - D+, DVC2C Channel-to-Channel Isolation between D+, D- and ID pins (in audio mode) DC bias (pin to GND) = 0.4V AC signal = 600mVp-p Freq. = 2kHz See Note 4 0V < VD < 3.6V, f = 2kHz OE_INT/ = 1 Measured at D+, D- pins, with respect to GND See Note 4 VBAT = 3.6V VBAT = 3.0V Driver Characteristics - Full Speed tR_FS tF_FS tR / tF VCRS tPLH tPHL Transition Time: Rise Time Fall Time Rise/Fall Time Matching Output Signal Crossover Voltage Propagation delay LOW to HIGH HIGH to LOW See Note 4 TAMB = 25C CL = 50pF to 125pF See Note 4 (TR/ TF) 4 4 90 1.3 12.5 12.5 20 20 111.11 2.0 18 18 ns ns % V ns ns
-60
dB
ZOUT_3S_D
High-Z State Output Impedance
300
k
Data Rate FI2C I2C signaling rate 100 100 400 200 kbps kbps
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MIC2555
Symbol TPDZ
Parameter Driver Disable to Tri-State delay (Full or Low Speed) Driver Tri-State to Enable delay (Full or Low Speed) Transition Time: Rise Time Fall Time Rise/Fall Time Matching Output Signal Crossover Voltage
Condition HIGH to OFF LOW to OFF See Note 4 OFF to HIGH OFF to LOW See Note 4 CL = 350pF See Note 4 (TR / TF)
Min
Typ
Max 15 15 15 15
Units ns ns ns ns
TPZD
Driver Characteristics - Low Speed tR_LS tF_LS tR / tF VCRS
TAMB = 25C 75 75 80 1.3 245 265 300 300 125 2.0 ns ns % V
Receiver Characteristics - Full Speed / Low Speed Differential Receiver tP_LH tP_HL Propagation delay LOW to HIGH HIGH to LOW See Note 4 LOW to HIGH HIGH to LOW See Note 4 D+, D-, ID, and VBUS to GND Human Body Model All pins Human Body Model 15 15 ns ns
Single-Ended Receivers tP_LH tP_HL ESD(3) VESD VESD Electro Static Discharge Voltage Electro Static Discharge Voltage 15 2 kV kV Propagation delay 18 18 ns ns
Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating range. 3. Specifications are for packaged product only. 4. Parameters are guaranteed by design. They are not production tested.
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MIC2555
Functional Diagram
VTRM CC+ C++
VBAT
VTRM
Voltage Doubler and 5V Regulator
VBUS
VDD_LGC INT/ SDA SCL RESET/ ADR_0 Serial Controller
VBUS Comparator ID Detector Interrupt Detector Pull-Up/Down Resistors ID
GPIO_1_TX MUX GPIO_0_RX DAT_VP_RX SE0_VM_TX OE_INT/
TXD RXD Diff TX
GPIO_2 D+ DGND_A
SE D+
GND_D
RCV
Pull-Up/Down Resistors
SE D-
Diff RX
MIC2555 Block Diagram
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M9999-060805 (408) 955-1690
Micrel, Inc.
MIC2555
Functional Description
The MIC2555 is designed to provide full USB On-TheGo (OTG) connectivity in mobile systems where low power and small size are key considerations. Intended for use in self-powered systems, the MIC2555 draws no current from VBUS for its operation, but will supply a minimum of 10mA at 5V to VBUS, from an on-chip charge pump, when operating as an A-device. The MIC2555 meets USB physical layer specifications while operating with logic supply voltages as low as 1.6V and battery voltages down to 3.0V. MIC2555 operation is controlled through an I C bus by reading and/or writing to registers within the MIC2555. Control registers are used to set the operational mode to USB, Audio or UART (`RS232' format). Other features include VBUS comparators for SRP detection and ID pin recognition of USB and non-USB peripherals. The MIC2555 minimizes collateral components, requiring only 4 external capacitors and two resistors. All USB required pull-up/pull-down resistors are on-chip. 15KV ESD protection on all pins exposed to user contact (VBUS, D+, D-, ID and GND) eliminates the need for external ESD transient protection devices. Definitions and Conventions
Car Kit IC NUT OTG SIE SE0 SRP USB USB-IF Serial Controller UPPER CASE Lower case
(1) 2
System Description
Overview: The MIC2555 OTG Transceiver provides the physical interface for ASICs, uPs and SOCs having an On-TheGo Serial Interface Engine (SIE) but lacking a physical interface capable of driving cables, or generating and detecting the necessary voltages to operate as a USB host. MIC2555 goes beyond the confines of the USB OTG standard and provides flexible communication between many kinds of digital devices. Point-to-point UART and Audio communications can also be accomplished using the MIC2555 and any and all of these formats can be utilized by a single system. All communications are accomplished via the D+ and DI/O pins. The information passed through D+ and D-, such as USB, UART, or audio, depends upon the mode of communication. The system controls the mode of communication through the MIC2555's control registers. Modes of Operation The MIC2555 OTG Transceiver has five distinct operating modes: * * * USB mode: Operates as a USB OTG transceiver. UART mode: Operates as a UART transceiver Audio mode: Operates as a passive device within the audio path, but actively monitoring for digital control signals.
2
= = = = = = = = = = = =
A non-USB target device Inter IC Bus (I2C) non-USB target device On-The-Go Serial Interface Engine Single Ended Zero Session Request Protocol Universal Serial Bus USB Implementers Forum Means the I C control function within MIC2555. IC pins Control Register Bits
2
USB mode The two modes of USB operation involve the way data is transferred between the SIE and the transceiver. These modes are: * DAT-SE0 mode:
- DAT_VP_RX .DAT: single ended data I/O SEO: detects or sends the SE0 - SE0_VM_TX condition. - RCV is not used
*
VP-VM mode:
- DAT_VP_RX VP: D+ data to transceiver output. VM: D- data to transceiver output. - SE0_VM_TX - RCV Output of the differential receiver.
Notes: 1. An `OTG Controller' is understood to be any integrated circuit, or system, possessing a built-in USB OTG Host/Device control function but lacking the USB physical layer interface.
Data flow direction:
Transmit Receive OE_INT/ = 0 OE_INT/ = 1
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Micrel, Inc. Conditions for USB mode: uart_en = 0 Speed = Low speed =0 Full speed = 1 UART mode There are two UART modes of operation: * Direct UART: - UART TX SE0_VM_TX pin, data is output on D- UART RX DAT_VP_RX pin receives UART data from
D+.
MIC2555 Power Management The transceiver's power modes are: Active power: All functions active, transceiver fully powered. Conditions: suspend = 0 pwr_dn = 0 Suspend power: The differential transmitter and receiver are turned off to conserve power but the USB interface is still active (i.e., pull-ups and pull-downs still active, VBUS generation on, etc.). Conditions: suspend = 1 pwr_dn = 0 Power Down: Only the serial interface is still active and the transceiver is able to detect SRP. The ID pin sensing may be turned on or off with a control bit in the control registers. Conditions: suspend = 1 pwr_dn = 1
Functions Powered Down By Control Bit
Differential Driver Differential Receiver UART TXD D+ interrupt comparators VBUS Comparators VTRM LDO VBUS output Internal biasing circuits and band gap reference Charge Pump off
*
Secondary UART: - UART TX GPIO_1_TX pin, data is output on D- UART RX GPOI_0_RX pin, received from D+.
Conditions for UART mode: uart_en = 1 speed = 1 uart_io = Direct UART = 0
Secondary UART inputs (GPIO) = 1
Note: It is not necessary to reset uart_io when switching from UART to USB mode; uart_io is deactivated when uart_en = 0, so its setting will not effect DAT_VP_RX or SE0_VM_TX's operation in USB mode. Audio Mode There is one mode of Audio operation. In audio mode, the MIC2555's D+ and D- outputs are Tri-Stated (high impedance) and the OTG controller or system components can send and receive audio signals via the D+, D- lines. The MIC2555 will monitor the D+ line for voltages crossing one of two levels, as a means of detecting a car kit interrupt signal. These interrupt events are captured and flagged by the Serial Controller. Conditions: uart_en = 0 OE_INT/ = 1 cr_int_sel = detect @ 3.0V = 1 detect @ 0.5V = 0 Note: The MIC2555 has no provision to connect or disconnect audio devices from the D+, D- lines, so the designer is cautioned to be sure that when the MIC2555 is operating as a data transceiver, no damage will ensue if the system's audio components are exposed to USB or UART digital signal levels.
Control Bit suspend
pwr_dn
cp_off

Power Management Table
Note: Suspend and Power-Down bits operate independently of each other. Activating Power-Down does not automatically invoke Suspend. For lowest power operation Suspend, Power-Down and Charge Pump OFF modes must be activated: Conditions: suspend = 1 pwr_dn = 1 cp_off = 1 11
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Micrel, Inc. Circuits still operating: ID detect and D- receiver continue to function. This includes the ID comparators, ID pull-up circuits, and D- data receiver. Serial Controller Block The Serial Controller manages MIC2555 operations. Turning ON/OFF features, changing operating modes, setting and selecting interrupts are all handled by the Serial Controller. MIC2555's Serial Controller 2 communicates with the OTG Controller as an I C slave using the SCL and SDA pins. The Serial Controller includes the following functions: * * * * * * Control registers Status registers Interrupt latches Interrupt enable registers Interrupt clear registers Interrupt generator
Session End 0.5V Session Valid 1.4V
MIC2555
VBUS Output Enable
Cap-
Cap+
Cap++
VBAT
Charge Pump and Regulator
VTRM 3.3V
2.3k
Charge VBUS
VBUS
VBUS Valid
4.4V
VBUS Charge Pump and 5V regulator The charge pump draws power from VBAT and boosts the voltage to the requisite 5V to power VBUS. This subsystem is actually a combination of a charge pump circuit and a control loop that gates the charge pump's oscillator. If the output voltage is below 5V, then the oscillator is ON; otherwise, the oscillator is gated OFF. The charge pump's maximum output is controlled by the magnitude of VBAT. When VBAT is at 3.0V, the charge pump is designed to support loads of at least 8 mA on VBUS. As VBAT increases, the maximum charge pump output current also increases. For proper operation the charge pump circuit requires 2 capacitors; one for the voltage doubler, connected between C- and C+, and a reservoir/filter capacitor between C++ and ground. The charge pump's nominal operating frequency is 200 kHz, which is set by an on-chip oscillator. A special feature of MIC2555 is that an external oscillator can drive the charge pump as well, allowing the designer to shift radiated noise away from sensitive frequencies when necessary. Also, when 5V power is not required from VBUS, the charge pump can be shut down to conserve power.
2.3k Discharge VBUS
68k
VBUS Circuitry
VBUS Resistors and Switches MIC2555 is able to: * * * * * charge up VBUS through a resistor initiate SRP pull down VBUS through a resistor to ground discharge VBUS before initiating SRP switch VBUS power from the charge pump ON/OFF
Dedicated bits in the control registers control all of these functions. Because these bits act independently, it is possible to have VBUS both charging and discharging at the same time. This situation will not harm the MIC2555. To prevent system leakage currents from biasing VBUS to a voltage that would mimic a session valid condition, the MIC2555 maintains a 68K resistor between VBUS and ground to insure that at no time will VBUS assume a floating condition.
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Micrel, Inc. VBUS Comparators VBUS Comparators monitor the voltage level of VBUS. As described in the USB On-The-Go Supplement, VBUS not only supplies power but also is used to signal various operational conditions as part of the SRP protocol. Depending upon the voltage on VBUS, three states of operation can be defined: * * * VBUS Valid Session Valid Session End.
RCV Single Ended Decoder VTRM Controlled by Register Bits 1.5k DAT_VP SE0_VM OE_INT/
MIC2555
1.5k
VBUS Valid Comparator This comparator is used by an A-device to determine whether the voltage on VBUS is at a valid level for operation. The minimum threshold for the VBUS valid comparator is 4.4V. Any voltage on VBUS below the threshold of the VBUS valid comparator is considered a fault. During power up, it is expected that this comparator's output will be ignored. Session Valid Comparator The session valid comparator determines when VBUS is high enough for a session to start. Both the A-device and B-device use this comparator to detect when a session is being started. The A-device also uses this comparator to indicate when a session is over. The session valid window for an A-device is 0.8 - 2.0V while the session valid window for a B-device is 0.8 - 4.0V. Because these ranges overlap the A-device window is typically chosen to service both requirements and a single comparator can be used. This is the case with MIC2555. Session End Comparator The USB OTG Supplement specifies that a B-device cannot initiate SRP unless VBUS is below the B-device Session End threshold of 0.8V. Monitoring VBUS with a comparator will give an exact and positive determination of when VBUS has dropped below 0.8V, but the USB OTG supplement allows that the 0.8V limit can also be inferred, by discharging VBUS through a low value resistor for a predetermined period. The MIC2555 provides both a session-end comparator and a discharging resistor. To accommodate either technique, the designer can use them individually or, in concert as he so chooses. Pull-up/down Resistors on D+, DMIC2555 supplies the pull-up and pull-down resistors for termination and signaling required by USB specifications. These resistors are integrated within the chip and switched into the circuit, as needed, via individual control bits in the control registers.
1.5k Controlled by Register Bits
1.5k
Resistors and Circuitry associated with D+, D- Pins
ID Detector The ID function, defined within the USB On-The-Go supplement, represents a new addition to the USB standard. It is used to detect the presence or removal of a peripheral device as well as to differentiate between USB and non-USB peripherals. ID is unique to the miniUSB connectors and receptacles. MIC2555's ID Detector is operational in both the Active and Suspended power modes, and differentiates between three conditions:
ID Pin Condition Floating Grounded Grounded through a Resistor Device Status No device present USB device present Non-USB device present VID VID > 0.85VBAT VID < 0.15VBAT 0.15VBAT < VID < 0.85VBAT
Here, `Grounded through a Resistor' means a resistor of a considerable value, typically 100k. The ID comparators are set to ignore the modest resistances contributed by the cables and connector contacts. That a non-USB device is present (ID = resistive) is inferred from the interrupt register by the indication of an interrupt (ID has changed state) and that neither ID = GND or ID = Float are true. Viewing the Interrupt source register will give the real time status of the ID comparator outputs. Viewing this register is necessary to determine the true state of affairs as insertion of the USB plug can produce multiple rail-to-rail transitions. These 13
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Micrel, Inc. will trigger both comparators and produce a conflicting result: ID = GND and ID = Float. The Interrupt source register contains the debounced steady state value of ID. After the nature of the newly connected device has been determined, activating a current source in series with the internal ID pull-up resistor can reduce power consumption caused by ID sensing. This is accomplished by clearing rcs_dis in Control Register 3. When the connected device is removed, and the ID pin is pulled HIGH by the current source (ID=GND is no longer true), MIC2555 automatically resets rcs_dis, disabling the current source.
VBAT Open = Reduced ID sensing current 4 A
MIC2555 Interrupt Detector When in Audio mode, the MIC2555 does not participate in the audio transmissions, but monitors the D+ line for interrupt pulses. If the Serial Controller is configured to flag interrupt pulses, the system controller can exchange both audio signals and digital information with the target device. MIC2555 is designed to detect two different interrupt pulses, those exceeding 3.0V and those crossing the 0.5V level. Under normal circumstances, the audio signal seen on D+ is transposed on a DC level and limited to voltage excursions between the 0.5V and 3.0V levels, so only interrupt pulses should cross these thresholds. Signaling is typically done with only one polarity pulse so MIC2555 is designed to monitor only one threshold at a time. Threshold selection is done with the cr_int_sel bit, and the interrupt (cr_int) can be set to trigger on pulses of either polarity. UART Mux System controllers with UART communication ability may or may not be able to route their UART signals through the VP, VM or DAT, SE0 pins. For those with independent UART connectivity, MIC2555 provides a secondary UART I/O port. The MUX, under direction of the Serial Controller, selects which UART I/O is used by the OTG controller. Condition: uart_io = 0 SEO_VM_TX = transmit DAT_VP_RX = receive uart_io = 1 GPIO_1_TX = transmit GPIO_0_RX = receive Differential Driver / Differential Receiver Operation of the Differential Driver and Differential Receiver is described in the tables below and on the following page. The register bits used in the column headings are described in the Serial Controller section of this data sheet.
100 k ID High 0.85x VBAT
ID
ID Low
0.15x VBAT
Closes to signal Peripheral 1k
ID Pin - Operational Diagram
VTRM VBAT powers VTRM, which supplies 3.3V power to the differential USB transmitter and the UART drivers and receivers. As VBAT drops below 3.4V, VTRM is no longer able to regulate and follows VBAT at about 0.1V less than VBAT. When this occurs, output drive levels for USB and UART are reduced accordingly.
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Micrel, Inc. USB mode: uart_en = 0 suspend 0 0 0 0 1 1 DIFF RX_SE0 TX_DAT TX_SE0 Z = = = = = dat_se0 0 0 1 1 0 1 OE_INT/ 0 1 0 1 1 1 RCV DIFF DIFF Z Z Z Z DAT_VP TX data SE_DP TX data DIFF SE_DP SE_DP SE0_VM TX data SE_DM TX data RX_SE0 SE_DM RX_SE0 D+ DAT_VP RX data TX_DAT RX data RX data RX data DSE0_VM RX data TX_SE0 RX data RX data RX data
MIC2555
Differential receiver output not (SE_DP) and not (SE_DM) DAT_VP and not (SE0_VM) not (DAT_VP) and not (SE0_VM) Tri-State
USB Transmit Operation USB Mode Inputs DAT_VP_RX SE0_VM_TX 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 D+ 0 1 0 0 0 1 0 1 Outputs D1 0 0 0 0 0 1 1 RCV unused unused unused unused undefined 1 0 undefined
DAT-SE0
VP-VM
The transceiver receives USB data from D+, D- lines when: Conditions: Uart_en = 0 OE_INT/ = 0 Operation of the DAT_VP_RX, SE0_VM_TX and RCV pins during receive is shown on the following page.
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Micrel, Inc. USB Receive Operation USB Mode Suspend 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Inputs D+ 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DAT_VP_RX undefined 1 0 undefined 0 1 0 1 0 1 0 1 0 1 0 1 Outputs SE0_VM_TX 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 1 RCV n/a n/a n/a n/a n/a n/a n/a n/a undefined 1 0 undefined n/a n/a n/a n/a
MIC2555
DAT-SE0
VP-VM
If the transceiver is in the DAT-SE0 mode, and the suspend bit has not been set, then the DAT_VP_RX pin always follows the output of the differential receiver during receive operation. The DAT_SE0 pin is not gated by the outputs of the single ended receivers. In the VP-VM mode, the RVC pin always follows the output of the differential receiver. The RVC pin is not gated by the outputs of the singled ended receivers. UART mode: uart_en = 1
suspend
0 1
Single-Ended Receivers The Single Ended Receivers detect the logic levels on the D+ and D- lines, and provide this information to the Single Ended Decoder. Single-Ended Decoder Behavior of the Single-Ended Decoder is dependent upon the power mode of the transceiver. If transceiver is in the Suspend power mode, and dat_se0 = 1 (DAT-SE0 mode), then the DAT_VP_RX pin will reflect the output of the D+ single ended receiver. This is necessary so that a controller connected to the transceiver can detect data pulsing while the transceiver is in suspended mode.
DAT_VP
SE_DP Z
SE0_VM
TX data Z
D+
RX data Z
DSE0_VM Z
Z = Tri-State
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MIC2555 VTRM can be used to supply small amounts of current to other system functions, typically 3 mA or less. However, trying to source more current can reduce output drive on D+, D- by stealing current from the differential driver. ID ID detects the arrival or departure of a peripheral device, and differentiates between USB and non-USB devices. To accomplish this, ID is pulled-up by a resistance of approximately 100 k connected to VBAT and the voltage at ID monitored by a set of comparators. When no device is present, ID is pulled high and NO DEVICE condition is reported. When a Mini-A plug is inserted into the system's Mini-AB receptacle, ID is connected to ground by the Mini-A plug, which triggers the MIC2555 to indicate a USB device is present. Non-USB peripherals use a modified Mini-A plug or nonstandard cable assembly with a resistor connected between ID and ground. When connected, this forms a resistor divider such that a voltage of approximately 1/2 VBAT appears at MIC2555's ID pin, indicating a non-USB device is present. Additionally, ID can be used to signal non-USB devices. This is accomplished by grounding ID through a low value resistor (~ 1 k), dropping the ID voltage from 1/2 VBAT to nearly zero, which can be detected by the attached device. This switch is activated by the id_gnd_out bit in Control Register 2. C-, C+, C++ C-, C+ and C++ are the capacitors required for charge pump operation. C- and C+ are the connections to the `flying' capacitor, which creates the pumping effect. C++ is the reservoir capacitor that stores the 5V supplied to VBUS when vbus_drv is asserted. Because the input source is a low voltage and the charge pump's regulator is set to limit VOUT to 5V, these capacitors need only be rated at 6 VDC, which helps reduce physical size and cost. GND_A, GND_D MIC2555 uses separate ground lines within the chip to isolate digital noise from analog signals. Ultimately, these two grounds need to be tied together. This is best done by having both grounds return separately to the power source and join at the bypass capacitor. RESET/ System reset. Returns all control register bits to their default settings. MIC2555 is not equipped with an internal power-on reset generator, and thus relies upon the system for its reset at power up.
Pin Descriptions
VBAT This pin is an input, and supplies power to the transceiver. Transceiver typical operational voltages are between 3.0 V VBAT 4.5V and 1.6V < VDD_LGC < VBAT. VDD_LGC This input is used to set the logic thresholds of the following logic signals: * * * * * * * * DAT_VP_RX SE0_VM_TX RCV OE_INT/ INT/ ADR0 RESET/ GPIO
Important Note: VDD_LGC can be at a voltage less than or equal to VBAT, but never higher than VBAT. Doing so will forward bias internal pad protection diodes and current will flow from VDD_LGC to VBAT. For this reason, systems should not allow VBAT to go to zero while VDD_LGC remains powered. This condition may damage the MIC2555, and could put a severe load on VDD_LGC as it attempts to power the MIC2555 and all other circuits attached to the VBAT line. VBUS This pin functions as both an input to, and output from, the transceiver. Unlike standard USB transceivers, however, the MIC2555 always derives its operating power from VBAT and never from VBUS. The MIC2555 will supply power to VBUS when acting as a host device and when petitioning another OTG, capable device to become the host. To do so the vbus_chrg bit is asserted. To power VBUS, as a host device, the vbus_drv bit is asserted. The difference between these two controls is vbus_chg applies VTRM (3.3V) to VBUS, where as vbus_driv uses the 5V charge pump output. While VTRM is sufficient for signaling purposes, it does not meet the 4.4V minimum for VBUS. VTRM VTRM supplies a regulated 3.3V to the D+, D- output drivers, pull-up resistors and other circuitry internal to the MIC2555. A small filter capacitor is required to insure the regulator remains stable under all operating conditions. A good quality 1F capacitor is sufficient for this purpose.
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Micrel, Inc. DAT_VP_RX, SE0_VM_TX, RCV DAT_VP_RX, SE0_VM_TX and RCV provide the data transfer interface between the system controller and MIC2555. RCV is an output only pin, supplying the output of a differential receiver monitoring the D+, Dpins, while DAT_VP_RX, SE0_VM_TX are bi-directional (I/O) pins and change function in accordance with different USB and UART mode selections. In UART mode, DAT_VP_RX and SE0_VM_TX are the primary data transmit and receive pins. In USB mode, the setting of the dat_se0 determines their action, as described in the tables below.
MIC2555 OE_INT/ The "output enable - interrupt bar" (OE_INT/) pin has three modes of operation, shown in the table below. Suspend modes are controlled by the oe_int_en bit found in Control Register 1.
OE_INT/ Operating Modes
suspend
0 1 1
oe_int_en
x 0 1
I/O
Input Input Output
Description
OE_INT/ acts as output enable, and controls direction of DAT_VP_RX, SE0_VM_TX, D+ and DOE_INT/ is an input, but does not control anything OE_INT/ is asserted low if interrupt condition exists
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Micrel, Inc. SCL, SDA The serial clock (SCL) and serial data (SDA) signals 2 implement a two-wire I C serial bus for control of the 2 MIC2555. As with all I C busses the MIC2555 shares a common external pull-up resistor on each line. INT/ The interrupt (INT/) pin is asserted while an interrupt condition exists. It is an open drain output so that it can be wire-ORed with other interrupt signals, and requires an external pull-up resistor to provide a logic output. The pull-up voltage must not be greater than VBAT. ADR0 Because some systems may have more than one 2 transceiver on the I C bus, OTG Transceivers have 2 been assigned four I C Address locations by convention. MIC2555 address: 01011xxb (Bit order: A6 A0)
MIC2555 GPIO_1_TX, GPIO_0_RX, GPIO_2 GPIO_0, GPIO_1, and GPIO_2 are general purpose I/Os that can be used as data ports or interrupt sources for the system controller, display drivers or power switches for actuators or annunciators. These GPIO have open drain outputs capable of sinking at least 10 mA, can be wire ORed together, and may be pulled above the MIC2555's operating supply voltage, but not beyond the 6V absolute maximum allowed. As logic inputs, the GPIO logic thresholds are standard CMOS thresholds set by VDD_LGC voltage. The GPIO Input Register is a read-only register and shows real time status of the GPIOs, independent of other I/O settings. The GPIO Output Register holds the desired output value for each I/O. Each I/O can act as an independent interrupt source and can be programmed for triggering on T F, F T, or both transitions simultaneously. The GPIO pins serve double duty as active signal pins when called into action by the appropriate control bit: GPIO_0 = Secondary UART Receive input. GPIO_1 = Secondary UART Transmit output. GPIO_2 = External charge pump oscillator input. Audio mode: D+ Stereo DD+ Mono DMic
The ADR0 pin and MIC2555's `dash number' control the `xx' of MIC2555's address, where -0 or -1 specifies the higher order bit's value: Part Number MIC2555BML-0 MIC2555BML-1 Where x = the state of ADR0 D+, DThe data plus (D+) and data minus (D-) pins output the USB data signals. When operating as a non-USB transceiver, the role of D+, D- change: UART mode: D+ = RXD D- = TXD Address Range 0x 1x
These are generally agreed upon, but are not mandatory.
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Serial Controller
Register Map
REGISTER NAME Vendor ID Product ID Control Register 1 Control Register 2 Interrupt Source Undefined Interrupt Latch Interrupt Mask False Interrupt Mask True Undefined Control Register 3 GPIO Output Enable GPIO Output GPIO Input Undefined GPIO Interrupt GPIO Mask False GPIO Mask True Notes: 1. 2. 3. 4. ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R/S R/C R/S R/C R/S R/C scl_en 0 0 rcs_dis 0 0 ext_osc 0 0 sess_end_en 0 0 cr_int_sel 0 0 id_det_off GPIO_2 GPIO_2 cp_off GPIO_1 GPIO_1 pwr_dn GPIO_0 GPIO_0 R/S R/C R/S R/C R/S R/C R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_2 GPIO_2 GPIO_2 GPIO_1 GPIO_1 GPIO_1 GPIO_0 GPIO_00 GPIO_0 scl_en rcs_dis ext_osc sess_end_en cr_int_sel id_det_off cp_off pwr_dn ACCESS R R R R R/S R/C R/S R/C R R/S R/C R/S R/C R/S R/C BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
x8D x05 xB0 see Note 1 x55 see Note 1 uart_io vbus_chrg cr_int uart_en vbus_dischrg bdis_acon (sess_end) bdis_acon (sess_end) bdis_acon (sess_end) bdis_acon (sess_end) oe_int_en vbus_drv id_float bdis_acon_en id_gnd_out se_dm test bit dm_pulldown id_gnd_in dat_se0 dp_pulldown se_dp suspend dm_pullup sess_vld speed dp_pullup vbus_vld
cr_int cr_int cr_int
id_float id_float id_float
se_dm se_dm se_dm
id_gnd_in id_gnd_in id_gnd_in
se_dp se_dp se_dp
sess_vld sess_vld sess_vld
vbus_vld vbus_vld vbus_vld
These values will change with chip revision level and are assigned by Micrel at the time of manufacture. All bits reset to zero, except those listed in WHITE, which reset to one. Register bits not listed are undefined. The upper five bits of the GPIO registers always read zero.
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Control Bit Locator
Control Bit bdis_acon, (sess_end) bdis_acon_en cp_off cr_int cr_int_sel dat_se0 dm_pull-down dm_pull-up dp_pull-down dp_pull-up ext_osc GPIO_0 GPIO_1 GPIO_2 id_det_off id_float id_gnd_in id_gnd_out oe_int_en rcs_dis scl_en se_dm se_dp sess_end_en sess_vld pwr_dn speed suspend test bit uart_en uart_io vbus_chrg vbus_dischrg vbus_drv vbus_vld Location Control Register 1 B4 B1 B7 B3 B2 B3 B1 B2 B0 B5 B0 B1 B2 B2 B5 B3 B4 B5 B6 B7 B4 B2 B4 B1 B0 B0 B1 B3 B6 B7 B7 B6 B5 B0 Control Register 2 Control Register 3 Interrupt Source B6 GPIO Interrupt
Serial Controller Register Bits
Example Table Format
Column Titles Field name Note: Size (bits) Access Register (1) Addresses Description
Access type "rd/s/c" denotes a field that can be read, set to 1 or cleared to 0. The register can be read from either of the Addresses indicated. When writing to the "set" Address, any 1s that are written cause the associated bit to be set. When writing to the "clr" (Clear) Address, any 1s that are written cause the associated bit to be cleared.
Device ID Registers
MSB -> Higher byte of two byte word LSB -> Lower byte of two byte word USB-IF Vendor ID number. Address 00h contains lower byte of Vendor ID. Address 01h contains upper byte of Vendor ID. A number unique to each manufacturer, for each device type produced. The manufacturer assigns this number. Address 02h contains lower byte. Address 03h contains upper byte.
vendor_id
16
rd
00h
product_id
16
rd
02h
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Control Register 1
Set & Clear speed suspend dat_se0 test bit bdis_acon_en 1 1 1 1 1 rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c set - 04h clr - 05h bit 0 bit 1 bit 2 bit 3 bit 4 1 set = 1 1 clr = 0 0 = USB Low Speed mode 1 = USB Full Speed mode 0 = Full power mode 1 = Low power mode 0 = VP-VM USB mode 1 = DAT-SE0 USB mode Not used 0 = No action. 1 = Attaches pull-up resistor to D+ after detecting SE0 condition and sets interrupt flag. 0 = OE_INT/ is an input. 1 = OE_INT/ becomes an output and is asserted LOW when interrupt occurs, if suspend = 1. If suspend = 0, pin remains an input. 0 = USB mode 1 = UART mode 0 = GPIO pins operate as standard GPIO. nd 1 = GPIO_0 = 2 UART RX nd GPIO_1 = 2 UART TX GPIO_2 = standard GPIO
oe_int_en uart_en uart_io
1 1 1
rd/s/c rd/s/c rd/s/c
bit 5 bit 6 bit 7
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Control Register 2
Set & Clear dp_pull-up dm_pull-up dp_pull-down dm_pull-down id_gnd_out vbus_drv vbus_dischrg vbus_chrg 1 1 1 1 1 1 1 1 rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c set - 06h clr - 07h bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1 1 set = 1 clr = 0
1 = Connect pull-up to D+ 1 = Connect pull-up to D1 = Connect pull-down to D+ 1 = Connect pull-down to D1 = Connect ID pin to ground 1 = Power VBUS with charge pump 1 = Discharge VBUS through a resistor 1 = Charge VBUS through a resistor
Control Register 3
Set & Clear pwr_dn cp_off 1 1 rd/s/c rd/s/c set - 12h clr - 13h bit 0 bit 1 1 1 set = 1 clr = 0
1 = Power Down mode. 1 = turns charge pump OFF. (Charge pump generates 5V for powering VBUS) 0 = ID comparators ON. 1 = Turns ID comparators OFF. Note: Powering down ID comparators does not shut off ID pin pull-up. Car Kit interrupt select: 0 = Detect < 0.5V level on D+ 1 = Detect > 3.0V level on D+ 0 = no action. 1 = When bdis_acon_en = 0, switches Bit 6 of the Interrupt Register to indicate Session End comparator status. 0 = Internal oscillator drives charge pump 1 = External oscillator drives charge pump (Input source = GPIO_2) 0 = Activate current source. Weak pull-up on ID pin. 1 = Disable (bypass) current source pull-up on ID pin. Strong pull-up on ID pin. 2 0 = I C clock line only transmits. 2 1 = Bi-directional I C clock line. Bi-directional clock is required if target device is to be able to control data rate by holding SCL low.
id_det_off
1
rd/s/c
bit 2
cr_int_sel
1
rd/s/c
bit 3
sess_end_en
1
rd/s/c
bit 4
ext_osc
1
rd/s/c
bit 5
rcs_dis
1
rd/s/c
bit 6
scl_en
1
rd/s/c
bit 7
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Interrupt Source Register
Interrupt Status vbus_vld sess_vld se_dp id_gnd_in se_dm id_float 1 1 1 1 1 1 rd rd rd rd rd rd rd - 08h bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 Indicates the current state of signals that can generate an interrupt. 1 = VBUS > 4.4V (VBUS valid comparator) 1 = 0.8V< VBUS< 2.0V. (Session valid comparator) 1 = D+ pin is HIGH 1 = ID pin grounded 1 = D- pin is HIGH 1 = ID pin floating If: bdis_acon_en = 1 1 = SE0 has been detected, transceiver asserted dp_pullup after detecting B-device disconnect. If bdis_acon_en = 0, sess_end_en = 1 1 = VBUS < 0.8V. (Session End comparator output = TRUE) 1 = car kit interrupt, D+ pin has seen a pulse above the interrupt level
bdis_acon (sess_end)
1
rd
bit 6
cr_int
1
rd
bit 7
Interrupt Latch 1
Interrupt Source Vbus_vld sess_vld se_dp id_gnd_in se_dm id_float bdis_acon (sess_end) cr_int 1 1 1 1 1 1 1 1 rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c set -0Ah clr - 0Bh bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Indicates which sources have interrupted. 1 = interrupt.
Interrupt Mask False
False Interrupt Mask Vbus_vld sess_vld se_dp id_gnd_in se_dm id_float bdis_acon (sess_end) cr_int 1 1 1 1 1 1 1 1 rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c set - 0Ch clr - 0Dh bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Enables interrupts on transition from TRUE to FALSE 1 set = 1, Interrupt on T F. 1 clr = 0, no interrupt.
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MIC2555
Interrupt Mask True
True Interrupt Mask vbus_vld sess_vld se_dp id_gnd_in se_dm id_float bdis_acon (sess_end) cr_int 1 1 1 1 1 1 1 1 rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c set - 0Eh clr - 0Fh bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Enables interrupts on transition from FALSE to TRUE. 1 set = 1, Interrupt on F T 1 clr = 0, no interrupt.
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MIC2555
GPIO Output Enable
Set & Clear GPIO_0 GPIO_1 GPIO_2 1 1 1 1 1 1 1 1 rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c set -14h clr - 15h bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1 1 set = 1, GPIO = OUTPUT. clr = 0, GPIO = INPUT.
GPIO Output
Set & Clear GPIO_0 GPIO_1 GPIO_2 1 1 1 1 1 1 1 1 rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c set -16h clr - 17h bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1 1 set = 1 at GPIO OUTPUT. clr = 0 at GPIO OUTPUT.
GPIO Input
Read Status GPIO_0 GPIO_1 GPIO_2 1 1 1 1 1 1 1 1 rd rd rd rd rd rd rd rd rd - 18h bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Read current state of GPIO input
GPIO Interrupt Latch
Interrupt Source GPIO_0 GPIO_1 GPIO_2 1 1 1 1 1 1 1 1 rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c set -1Ah clr - 1Bh bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Indicates which sources have interrupted. 1 = interrupt.
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GPIO Interrupt Mask False
Set & Clear GPIO_0 GPIO_1 GPIO_2 1 1 1 1 1 1 1 1 rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c set - 1Ch clr - 1Dh bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Enables interrupts on transition from TRUE to FALSE 1 set = 1, Interrupt on T F. 1 clr = 0, no interrupt.
GPIO Interrupt Mask True
Set & Clear GPIO_0 GPIO_1 GPIO_2 1 1 1 1 1 1 1 1 rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c rd/s/c set - 1Eh clr - 1Fh bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Enables interrupts on transition from FALSE to TRUE. 1 set = 1, Interrupt on F T. 1 clr = 0, no interrupt.
Note:
.Access type "rd/s/c" denotes a field that can be read, set to 1 or cleared to 0. The register can be read from either of the Addresses indicated. When writing to the "set" Address, any 1's that are written cause the associated bit to be set. When writing to the "clr" (Clear) Address, any 1s that are written cause the associated bit to be cleared.
Example Serial Controller Register Settings
Example Location Target register `Set' register Target register `Clear' register Target register Condition Initial state Data loaded into `set' register Resulting state Data loaded into `Clear' register Resulting state BIT 7 0 1 1 1 0 BIT 6 0 0 0 0 0 BIT 5 1 0 1 0 1 BIT 4 0 0 0 0 0 BIT 3 1 1 1 1 0 BIT 2 0 0 0 0 0 BIT 1 0 0 0 0 0 BIT 0 0 0 0 0 0
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PCB Layout Recommendation
Although the USB standard and applications are not based in an impedance-controlled environment, a properly designed PCB layout is recommended for optimal transceiver performance. The suggested PCB layout hints are as follows: * * Match signal line traces (VP/VM, D+ D-) and try to keep them as short as possible. For every signal line trace width (w), separate the signal lines by 1.5-2 widths. Place all other traces at >2w from all signal line traces. Control signal line impedances to 10%. Keep Rseries as close to the IC as possible, with equal distance between Rseries and the IC for both D+ and D-.
* *
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MIC2555
Package Information
24-Pin MLF (ML)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2004 Micrel, Incorporated.
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